1. Field of the Invention
The invention generally relates to run length limited (2,7) coding schemes often used in data storage and retrieval systems to increase the storage capacity of such systems and minimize the effects of detection errors when retrieving data. More particularly, the invention relates to methods and apparatus for encoding and decoding data to and from a (2,7) format via the construction and implementation of state machines which convert RLL (2,7) variable length fixed rate codes into state dependent fixed length fixed rate codes.
2. Description of the Related Art
Disk drive manufacturers are constantly striving to produce disk storage systems with the lowest cost per megabyte. This is to keep pace with the computer user's desire for more affordable disk space to store more programs and databases, and to archive large data files.
Present disk drive storage capacities can be increased three ways; by increasing the track density, increasing the number of read/write heads and disk surfaces, or by increasing the number of bits stored per inch. The first two approaches require a substantial amount of mechanical development and are therefore expensive. The third approach is the least expensive and can be achieved by modifying the way a disk data separator encodes and decodes data.
A method for increasing the amount of data recorded on disks or similar media or the rate at which data can be reliably transmitted through a channel is known as Run-Length Limited (RLL) coding.
RLL codes represent binary data in a magnetic medium by the presence or absence of magnetic transitions within slots of uniform width. Transitions are separated by a minumum of d slots to prevent intersymbol interference but not more than k slots which is required for self-clocking purposes. The codes may be referred to as (d,k) limited codes.
The run-length limited (RLL) (2,7) code is popular with disk drive manufacturers because it offers low intersymbol interference and has good error recovery properties. If there is an error in the readback signal the code corrects itself after a short run of correct code bits.
U.S. Pat. No. 3,689,899 to P. A. Franaszek, hereby incorporated by reference, describes a method for encoding and decoding a (2,7) code using logic blocks such as counters, memory elements, shift registers and gates. The data codes are variable length fixed rate codes. The coding rate for the (2,7) code is 2:1 (two code bits for each data bit) and the memory element containing the data dictionary consists of 7 variable length words, with lengths varying from 2 to 8 bits.
The prior art control logic, as taught in the U.S. Pat. No. 3,689,899 patent, required to encode and decode a variable length fixed rate (2,7) code, is embedded in the aforementioned logic blocks. The control logic has to determine when a bit string in the input shift register is a word in the (2,7) data dictionary. Care must be taken to allow enough time between shifting and, encoding or decoding to handle the variable length words. When a valid data string is found, the control logic initializes a counter with the length provided by the data dictionary, loads the output shift register with the coded or decoded value and shifts out the code/data at the 2:1/1:1 rate. Concurrently, the input shift register is being loaded with the next data/code bits from the bit stream at a 1:1/2:1 rate e.g., for decoding; for every data bit shifted out, two code bits are shifted in).
It has been determined that it would be desirable to reduce the amount of logic and timing signal constraints required to implement a variable length fixed rate (2,7) code while retaining the increased storage capacity benefit and error recovery features of such codes.